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Very simple ACDC circuit, Transient Initialization

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Hi, I'm generating a very simple circuit in "Electrical circuits (cir)", a capacitor in parallel to a DC voltage source, 2 nodes only, GND and 1. I want to see the voltage across the cap in time. So I add a Time Dependent study, but the voltage is always constant. I've tried to change simulation step or use a Transient Initialization study but it didn't work.

Similarly, if I use a sinusidal voltage gen, the voltage across the capacitor is constant isntead of a sinusoid


0 Replies Last Post 17 janv. 2022, 11:38 UTC−5
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Hello raffa

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